Research Framework — Updated May 26, 2026
Node Expansion
Protocol
A repeatable engine for discovering supply chain bottlenecks before capital markets price them. The process is the asset — each node is a falsifiable output, not a fixed conclusion.
MasicotAI
v6.0 — Internal · May 2026
Q1
Physical Inputs
What materials or sub-processes does this node require? How concentrated is that supply?
Q2
Co-Purchases
What else ships in the same BOM or procurement event on a 1–3Q lag?
Q3
Constraint Migration
When this bottleneck loosens, where does the constraint move next in the stack?
Q4
Supplier Concentration
How many vendors are qualified? What is the switching cost and re-qualification timeline?
Q5
Economic Co-Travelers
Who benefits from the same demand wave via a separate causal chain — and gets dismissed as consensus?
Q6
Demand-Curve Position
A bottleneck can be real and late. What quantifiable metric says this is early vs. mature — and is it still climbing?
2024 — resolved
CoWoS Packaging
Primary acute bottleneck. TSMC capacity fully allocated, Blackwell shipments gated.
2024–2025 — missed
HBM Memory
SK Hynix ~80% qualified share. Upstream input to CoWoS, not adjacent to it.
2025 — missed
Server CPUs
BOM co-purchase with GPU racks. 2–3Q lag from GPU capex surge. Q2 not asked.
2025–2026 — live now
Substrates + Optical
ABF 98% Ajinomoto IP. NVIDIA $4B optical bet signals photonics as gating factor.
2027+ — forming now
Photomasks · Metrology · High-NA
Japan duopoly on EUV mask blanks. KLA ~58% process-control monopoly. Qualification time the binding constraint.
What this framework does
—Every major supply chain bottleneck has upstream dependencies, downstream demand consequences, and adjacent components traveling with it. Five questions force systematic mapping of all dimensions before an investment view is formed.
—Two historical misses — server CPUs and HBM memory — are documented as worked examples showing the exact question that wasn't asked. Both were inside the AI infrastructure thesis perimeter. Neither required proprietary data to catch.
—The methodology is the asset, not any single node. Each node is a falsifiable output of the engine. Photomasks may be right, or simply the first test of a larger bottleneck-discovery process.
Three distinct failure modes
01Upstream constraint failure — Q1 not asked. HBM is physically inside the CoWoS package. Not asking what a node physically requires left the most acute bottleneck unmapped despite being inside the primary thesis.
02Downstream propagation failure — Q2 not asked. Server CPUs ship in the same rack as GPUs. Not tracing bill-of-materials co-purchases produced a 2–3 quarter lag miss on a demand surge that was arithmetically predictable.
03Visibility bias — Q5 not asked. Micron was dismissed as too obvious. The framework now forces an explicit check on economic co-travelers that get underweighted precisely because they're visible.
The binding constraint is usually qualification, not capacity
Across CoWoS, HBM, and ABF, the recurring lesson is that qualified supply — not nameplate capacity — is what binds. A new mask blank factory built tomorrow does not add supply until its output is qualified into a fab's process, which takes months to years. This is why Q4 has two halves that must be assessed separately: how many suppliers are qualified today (static concentration), and how hard it is to add or switch suppliers (the qualification moat). HBM had three suppliers on paper but 12–18 month qualification — and the qualification half is the half that mattered. When assessing any node, weight the qualification timeline as heavily as the supplier count.
Q6 — Reading demand: the evidence ladder
A bottleneck can be real and late. The VRT lesson: a name found after a 7x run can still be early if the demand curve has years left — what matters is the runway ahead, not the chart behind. But "still early" is the most dangerous phrase in investing, so it must be earned with a quantifiable, climbing metric — not a vibe. Score every demand signal by evidence tier: ① Narrative (keynotes, announcements — sentiment only) → ② Capex guidance (board-approved but cuttable) → ③ Binding commitment (multi-year agreements, prepayments, sold-out allocations) → ④ Capital against the commodity (a buyer pre-funding supply rather than ordering — the highest-conviction signal, because the party with the most information is writing the check). Terafab is tier ① until a tool order exists. HBM sold-out-through-2027 is tier ③. NVIDIA's $4B into optical is tier ④. Noise becomes signal only when it climbs the ladder.
The three research buckets
AAcute — already binding and increasingly priced: optical interconnects, CoWoS substrates, power distribution, data center construction. Alpha is decaying as consensus forms.
FForming — signal building but not yet acute: photomasks, High-NA ecosystem, advanced metrology, EDA compute load. The current research focus.
IInvisible — where the most research time belongs: who makes the quartz, the pellicles, the mask writers, the inspection tools. What material has only two global suppliers? What has >80% share but a <$5B market cap?
Discipline against survivorship bias
!"Obscure + concentrated" is necessary but not sufficient for "next bottleneck." The HBM-in-2023 narrative is visible because it worked — the upstream niche suppliers where the constraint never propagated, or got engineered around, are invisible by definition.
!Q3 (constraint migration) is the discipline check: the constraint must actually bind and stay bound. Some obscure concentrated suppliers are obscure because they don't matter much. Deep concentration plus a binding, durable constraint — not concentration alone — is the signal.
Server CPUs
misseddownstream propagation failureQ2 not askedresolved 2025
Why this was missed
CoWoS was the identified thesis node. CPU is co-purchased in the same server bill of materials — every GPU rack requires host CPUs. Q2 was never asked. The demand signal was visible in hyperscaler capex guidance 2–3 quarters before the shortage materialized.
Q1 — Physical inputs
What does this node require?
Silicon wafers (same 300mm supply chain as GPUs), advanced packaging (TSMC N3/N5 for AMD Epyc, Intel Xeon on own fabs), DRAM for cache. Competes directly with GPU for TSMC fab allocation — no unique input of its own.
Q2 — Co-purchases missed
What travels in the same BOM?
Every GPU server requires 1–2 host CPUs. Hyperscaler rack procurement is a single BOM event. GPU capex surge 2023–2024 arithmetically implied CPU demand surge 2024–2025 on a 2–3 quarter lag. Signal was in AMD/Intel server order books and ODM rack configuration disclosures.
Q3 — Constraint migration — corrected sequence
HBM was the leading signal, not CPU
Actual propagation order:
- HBM tightness first — designed in 18–24 months before launch
- GPU supply constrained as result
- Rack deployment surge followed GPU availability
- CPU demand spike last — 2–3Q behind rack deployment
↑ corrected May 2026
Q4 — Supplier concentration
Three architectures, not a duopoly
- AMD (Epyc) — took significant x86 share 2023–2025 on perf/watt
- Intel (Xeon) — x86 incumbent, defending on ecosystem depth
- ARM — distinct architecture. Qualified via AWS Graviton, Ampere, NVIDIA Grace. Competes on efficiency for inference. Hyperscalers absorbing switching cost deliberately.
Signal that was available
AMD/Intel server CPU guidance Q4 2023–Q2 2024 showed order acceleration. ODM build plans disclosed rack CPU-to-GPU ratios. HBM tightness in SK Hynix earnings was the earliest leading indicator — visible 2–3 quarters before CPU shortage.
Portfolio implication — Intel vs ARM sizing
Holding ARM (underweight) alongside Intel (overweight) is an implicit architectural bet. AMD took significant x86 share through 2025. ARM's data center qualification pipeline expanding through 2026 is the key monitoring variable. Make the bet explicit before the market forces the question.
HBM Memory
missedupstream constraint failureQ1 + Q4 not askedphysically inside CoWoS
Why this was missed
HBM is bonded directly onto the logic die inside the CoWoS package — a mandatory physical input, not an adjacent component. Q1 was never asked. The SK Hynix qualification concentration meant supply was structurally tighter than headline memory market data suggested. Epoch AI confirms: advanced packaging constrained AI production first in late 2024, HBM bottlenecks followed through 2025.
Q1 — Physical inputs missed
HBM is inside CoWoS — not adjacent
CoWoS requires: silicon interposer (TSMC), logic die (TSMC fab), and HBM stacks bonded via Through-Silicon Vias. HBM cannot be substituted mid-package. It is mandatory — removing it makes the product non-functional. Closest miss to the primary thesis node.
Q2 — Co-purchases
Design-time lock-in, not procurement-cycle
HBM procurement locked at chip design time — NVIDIA specifies HBM vendor per SKU 18–24 months before product launch. This is why HBM tightness appeared earliest in the propagation chain, predating the CPU shortage by 2–3 quarters. All three major suppliers now effectively sold out through 2026.
Q3 — Constraint migration
HBM4E qualification cycle already forming
HBM3E tightness migrates to HBM4 qualification risk for Rubin (2025–2026). Samsung now qualified for Rubin after HBM3E yield recovery. Micron qualified for Rubin CPX inference tier, excluded from flagship. HBM shortage confirmed through 2030 by SK Hynix Chairman. HBM4E expected at 40% of mix by 2027 — next full qualification cycle underway.
Q4 — Supplier concentration missed
Three suppliers on paper, one dominated in practice
- SK Hynix ~57% — NVIDIA primary, flagship Rubin with Samsung
- Samsung ~17–28% — recovered from HBM3E yield failures, Rubin-qualified
- Micron ~21% — excluded from flagship Rubin, qualified for Rubin CPX
Signal that was available — and still is
SK Hynix earnings 2023–2024 explicitly discussed HBM allocation to NVIDIA. Samsung HBM3E yield issues in Korean trade press. Now: memory ~30% of hyperscaler AI spending. HBM TAM projected at $100B by 2028. Thesis evolved from cycle recovery to structural supercycle — it is not over.
Q5 — Economic Co-Traveler
Discovered — own node now
Co-traveler
Micron (MU) — the US-listed name riding the same HBM demand wave through a separate causal chain. Not a supplier to HBM; a producer of it, benefiting from the identical structural driver.
Underowned?
This was the original Q5 miss — dismissed as too-obvious cyclical memory coming out of the 2022–2023 downturn. Now has its own node tab. Preserved as the worked example that motivated adding Q5 to the framework.
Q6 — Demand-Curve Position
Tier ③ — Binding commitment
Runway
Mid — climbing ↑
Metric
HBM layers per stack: 8 → 12 → 16. Memory share of hyperscaler AI spend rose from ~8% (2023) to ~30% (2026). Each layer increase multiplies wafer area and inspection passes per die.
Evidence
Sold out through 2026, multi-year agreements signed, NVIDIA prepaying allocation (tier ④ behavior on the margin). Climbing, not flattening — but late enough that consensus has formed.
CoWoS Organic Substrates
live — acuteupgraded urgency May 2026ABF single point of failureJapan + Taiwan concentrated
Thesis — upgraded May 2026
TSMC targeting 140,000 CoWoS wafers/month by end-2026 — a 4x increase in two years — yet demand continues to outstrip even that expansion. The organic substrates beneath each package are now the pacing constraint. ABF substrate market hit $7.19 billion with Ibiden, Shinko, and Unimicron operating at near-full utilization. And critically: Ajinomoto controls 98% of ABF IP licensing rights — the US has zero independent ABF source. This is a single point of failure for US semiconductor manufacturing that almost nobody is discussing.
CoWoS Target
140K
wafers/month end-2026
vs 2024 baseline
4×
capacity increase in 2 years
ABF Market 2026
$7.2B
near-full utilization
ABF IP Control
98%
Ajinomoto — zero US alternative
Q1 — Physical inputs deepening
ABF — a monopoly inside the bottleneck
Ajinomoto Build-up Film (ABF) laminate: Ajinomoto holds 98% of IP licensing rights granted to a handful of East Asian companies. The US has no independent ABF source — it relies entirely on external supply. Ajinomoto has plans to increase ABF output ~50% by 2030, but current supply is the pacing item for the entire CoWoS expansion. Photomask production — another unheralded niche — also under pressure at this layer.
Q2 — Co-purchases
Substrates pace the entire assembly set
Substrates procured alongside silicon interposers and HBM as a package assembly set. At 6–9 month lead times — longer than silicon die lead times — substrates are the pacing item as TSMC scales toward 140K wafers/month. Even ultra-high-layer-count system boards hosting CoWoS packages are now in shortage, requiring premium CCL grades currently constrained.
Q3 — Constraint migration
Migrates to ABF film, then photomask production
If substrate supply tightens further: constraint migrates first to ABF laminate film (Ajinomoto monopoly), then to substrate drilling/plating equipment. Watch Ibiden and Shinko capex announcements as leading indicators. Longer term: photomask supply for High-NA nodes is the next layer down — see the Forming node tab.
Q4 — Supplier concentration
Japan-dominant, re-qualification required
- Ibiden (Japan) — primary for advanced AI substrates, TSMC qualified, new fabs with govt support
- Shinko Electric (Japan) — #2, TSMC qualified, expanding
- Unimicron (Taiwan) — constructing new ABF facilities, boosting output through 2025–2026
- Nan Ya PCB (Taiwan) — expanding with client pre-payments
US strategic exposure
No US company manufactures ABF or the substrates built from it. This is a direct dependency on Japan — a single seismic event, regulatory action, or diplomatic disruption cascades immediately into the entire US AI chip supply chain. CHIPS Act does not address this layer. A recent Convergence Analysis report specifically flagged ABF sourcing as a single point of failure requiring a US-Japan partnership framework.
Q5 — Economic Co-Traveler
Underowned — but offshore
Co-traveler
Ajinomoto (TYO: 2802) — a food company that is the 98% IP owner of ABF. The purest co-traveler in the framework: nobody screens a seasonings maker as an AI play, yet it sits at a single point of failure for the entire packaging stack. Also Ibiden, Shinko on the substrate layer itself.
Underowned?
Deeply — but all Japan-listed. This is where the framework's best finding collides with the US-mandate constraint. No clean US-listed expression exists; accessing it requires ADRs or stepping offshore. The honest answer is the alpha here is real and largely inaccessible without expanding the mandate.
Q6 — Demand-Curve Position
Tier ③ — Binding commitment
Runway
Mid-early — climbing ↑
Metric
CoWoS wafers/month: ~75K → 140K target by end-2026. ABF substrate market at $7.2B, near-full utilization. Substrate area per package rising as die sizes grow. Demand outstrips even the 4x capacity expansion.
Evidence
Suppliers expanding on client pre-payments (Nan Ya PCB), Unimicron constructing new ABF facilities against committed demand. Tier ③ — capacity reservations, not just guidance.
Optical Interconnects / Silicon Photonics
live — new node May 2026NVIDIA $4B signalcopper wall reachedindium concentration risk
Why this node is now confirmed
In March 2026, NVIDIA invested $2B each in Coherent and Lumentum with multiyear purchase commitments — explicitly to secure priority access to scarce optical capacity. When NVIDIA pre-commits capital rather than placing purchase orders, it is the same signal as their HBM investment: the commodity market cannot supply what they need. Networking — not compute — is increasingly the primary bottleneck in large AI clusters, directly impacting GPU utilization and cost per million tokens.
NVIDIA Optical Bet
$4B
Coherent + Lumentum, Mar 2026
Broadcom Switch Silicon
>80%
high-end switching market share
Interconnect Power
30%
of cluster power, early 2025
Copper reach @ 224G
<1m
physics limit driving optical transition
Q1 — Physical inputs watch
Indium phosphide — the new geopolitical chokepoint
Laser chips for optical interconnects require indium phosphide (InP) substrates. China holds a dominant position in global indium supply — a geopolitical risk US-based manufacturing investment alone cannot resolve without diversified upstream materials sourcing. This is the helium/Hormuz pattern: physical material concentration that a diplomatic resolution doesn't fix on its own timeline.
Q2 — Co-purchases
Every GPU cluster at scale needs this now
At 224 Gbps signaling, copper reach shrinks to under one meter — physics, not preference, is forcing the transition to optical. Co-packaged optics (CPO) are now being integrated directly into switch packages (Broadcom Tomahawk 6-Davisson). Every new hyperscale cluster deployment at 100K+ GPU scale requires optical interconnect — this is a mandatory BOM item for the current generation.
Q3 — Constraint migration
From pluggable modules toward co-packaged optics
Constraint migrates from discrete optical transceivers toward co-packaged optics (CPO) integrated at the chip package level — a more complex supply chain requiring TSMC-class packaging expertise. NVIDIA's roadmap follows TSMC's COUPE platform in three stages, with the second generation moving into CoWoS packaging with co-packaged optics at 6.4 Tb/s. This pulls the optical constraint back into the CoWoS packaging tier.
Q4 — Supplier concentration HBM pattern
Two concentration points: lasers and switching silicon
- Laser chips: Lumentum, Coherent, II-VI — NVIDIA pre-allocating capacity, pushing competitors' delivery timelines past 2027
- Switching silicon: Broadcom >80% of high-end switching, PAM4 DSPs in virtually every 800G and 1.6T transceiver
- Module assembly: Chinese manufacturers dominant — separate geopolitical exposure
- Marvell — acquired Celestial AI ($3.25B) for Photonic Fabric technology, AWS-backed
Bull case
Physics mandate — copper wall reached at 224G, optical is not a choice at hyperscale
NVIDIA $4B supply chain investment telegraphs structural shortage, not cyclical tightness
Broadcom switching silicon monopoly mirrors HBM concentration — same moat structure
CPO transition pulls optical into CoWoS packaging — doubles down on TSMC's packaging moat
US-listed plays available: Broadcom (AVGO), Marvell (MRVL), Lumentum (LITE), Coherent (COHR)
Bear case
Indium concentration in China — geopolitical supply risk with no near-term domestic alternative
Standards fragmentation — NVIDIA, Broadcom, and Arista pursuing different CPO architectures
Hyperscalers developing internal optical capabilities — Google, Amazon reducing vendor dependency
Module assembly concentrated in China — tariff and export control exposure on finished goods
Watch: CPO Standardization
Does industry coalesce on one CPO architecture or fragment? Standardization determines which suppliers capture the full TAM.
Watch: NVIDIA Rubin Optical BOM
When Rubin rack configurations are disclosed, the optical content per rack determines the immediate supply pull.
Watch: Indium Supply Diversification
Any US or allied-nation indium refining investment is a leading indicator that the supply chain risk is being addressed.
Q5 — Economic Co-Traveler
Mixed — consensus + hidden
Co-traveler
Consensus: Broadcom (AVGO), Marvell (MRVL) — switching silicon, well-covered. Underowned: Lumentum (LITE) and Coherent (COHR) — the laser-chip names NVIDIA just pre-funded; still screened as legacy telecom-optics rather than AI plays by much of the market.
Underowned?
Split. The switching-silicon layer is discovered (AVGO is consensus). The laser/component layer is the truer Q5 expression — and the $4B NVIDIA commitment is the catalyst forcing re-rating. All US-listed, which fits the mandate cleanly.
Q6 — Demand-Curve Position
Tier ④ — Capital against commodity
Runway
Early — climbing ↑
Metric
Interconnect share of cluster power: ~30% and rising. Copper reach collapses below 1m at 224G — a physics wall forcing optical adoption. CPO integration just beginning; pluggable-to-CPO transition is a multi-year curve barely started.
Evidence
Highest tier available: NVIDIA committed $4B of capital to secure optical capacity in March 2026 rather than placing orders. When the best-informed buyer pre-funds supply, the demand curve is early and steep.
Micron Technology (MU)
liveNasdaq: MUonly US HBM suppliermissed on entry — thesis ongoing
The visibility paradox — Q5 failure
Micron was too obvious. Coming out of the worst DRAM downturn in a decade, buying a deeply cyclical memory name felt like a consensus trade. The instinct to find differentiated plays suppressed the name most directly in the AI demand blast radius. Visibility was mistaken for lack of edge. This is what Q5 is designed to catch.
FQ2 2026 Revenue
$23.9B
+196% YoY
FQ3 Guidance
$33.5B
81% gross margin
HBM TAM by 2028
$100B
Micron projection
Shortage Duration
2030
SK Hynix Chairman forecast
Q1 — Physical inputs
What does Micron require?
300mm silicon wafers, advanced etch/deposition (Lam, AMAT), TSV bonding for HBM (yield-sensitive). HBM uses 3x wafer area vs DDR5 — competes directly for fab capacity. US fabs in Idaho and Virginia (CHIPS Act recipient) expanding through 2027–2028.
Q2 — Co-purchases the obvious miss
Memory is mandatory in every AI rack
No GPU rack without DRAM. No CoWoS package without HBM. The demand wave was visible from GPU capex commitments — memory required one propagation step that never got asked. HBM locked at design time (18–24 months). DDR5 with server CPUs (1–2Q lag). NAND for data center SSDs and KV cache for inference. Memory now ~30% of hyperscaler AI spending vs 8% in 2023.
Q3 — Constraint migration
Two migration paths from here
- Upward: HBM4E qualification cycle for 2027 platforms already forming
- Sideways: DDR5 tightening as HBM consumes wafer capacity — every HBM wafer removes DDR5 from supply
- Risk: Idaho/Virginia fabs online 2027–2028 — potential oversupply if AI demand normalizes faster than expected
Q4 — Supplier concentration
Third in HBM, first in US geopolitics
SK Hynix 57%, Samsung 17–28%, Micron 21% — but Micron is the only US-domiciled HBM supplier. CHIPS Act funding and US government procurement preference create structural tailwind independent of market share. Excluded from flagship Rubin; qualified for Rubin CPX inference tier. Inference may be the structurally better position as workloads scale.
Bull case
Only US HBM supplier — geopolitical tailwind independent of market share competition
HBM shortage through 2030 — a capex schedule, not a forecast
Inference tier positioning may be structurally correct as inference dwarfs training at scale
CHIPS Act backstop partially de-risks the $20B+ capex build
$33.5B FQ3 guidance at 81% margins — not speculative, earnings happening now
Bear case
Excluded from flagship Rubin — SK Hynix and Samsung locked in as primary HBM4 suppliers
Classic capex overshoot — Idaho/Virginia online 2027–2028, potentially into softer demand
196% YoY growth creates brutal comparison problem as base normalizes
China revenue restrictions impacting non-HBM segments
Q5 — Economic Co-Traveler
This node IS the Q5 case
Co-traveler
Micron is itself the worked example of Q5. It rode the HBM/memory demand wave through a separate causal chain from the GPU/CoWoS thesis — and was dismissed precisely because it was a visible, consensus, cyclical name. The framework's fifth question exists because of this miss.
Underowned?
No longer underowned — but the lesson is the discipline, not the ticker: visibility is not a disqualifier in a structural shift. The next Q5 co-traveler will also feel too obvious. That feeling is the signal to check, not skip.
Q6 — Demand-Curve Position
Tier ③ — Binding commitment
Runway
Mid — climbing, watch 2027 ↑
Metric
HBM revenue run-rate and gross margin: 81% guided FQ3. Memory share of AI spend 8%→30%. The runway marker to watch is the Idaho/Virginia fab ramp (2027–2028) — new supply could flatten the curve if demand normalizes.
Evidence
HBM sold out through 2026, multi-year agreements. But Micron's own capex is the bear marker: it builds into the demand curve, and the curve's position in 2027 determines whether that's prescient or an overshoot.
Power Delivery & Cooling
liveCPU miss pattern repeatingUS-listed exposure available800V architecture shift underway
Thesis
Blackwell and Rubin draw 10–20x the power of prior GPU generations. Every rack deployment pulls through voltage regulators, power semiconductors, and liquid cooling on a 1–2 quarter lag. An 800V architecture shift is now underway — NVIDIA pushing 800V while hyperscalers prefer ±400V — creating a qualification and component divergence that adds supply complexity beyond simple demand growth.
Q1 — Physical inputs
SiC and GaN — constrained raw materials
SiC and GaN wafers for power semiconductors. Copper and aluminum for busbars and cold plates. Dielectric fluids for immersion cooling. GaN expected to play critical role in 800V-to-low-voltage conversion where high switching frequency is required. Suppliers: Infineon, Texas Instruments, Navitas actively advancing GaN solutions for AI rack architecture.
Q2 — Co-purchases still underpriced
Every rack needs this — mechanical BOM item
Every GPU rack BOM includes: voltage regulators (Monolithic Power Systems, Vicor), power distribution units, liquid cooling loops or immersion tanks. 1–2 quarter lag behind GPU deployment. Vertiv and Eaton are system integrators capturing the surge. Same analytical pattern as the CPU miss — the market is still pricing this as cyclical infrastructure spend, not structural constraint.
Q3 — Constraint migration
Migrates to grid; architectural divergence adds complexity
Power delivery constraint migrates to grid interconnection — queues now exceeding 2,100 GW, surpassing total US grid capacity. 30–50% of planned 2026 data center capacity projected to slip to 2028. Architectural differences between NVIDIA 800V and hyperscaler ±400V systems extend adoption timeline to 2027–2030+, meaning this is not a short-term adjustment.
Q4 — Supplier concentration
Fragmented but lead-time constrained
- Voltage regulators: MPS, Vicor, Renesas
- Liquid cooling: Vertiv, Alfa Laval, CoolIT Systems
- Power semiconductors: Infineon, ON Semi, Wolfspeed, Navitas
Q5 — Economic Co-Traveler
Partly discovered
Co-traveler
Discovered: Vertiv (VRT) — already re-rated, the VRT $69→$300 story is the template. Less crowded: Monolithic Power (MPWR), Vicor (VICR) on voltage regulation; Navitas on GaN. The power-conversion layer is less consensus than the cooling-integrator layer.
Underowned?
Vertiv is the cautionary tale — the co-traveler that already ran, proving the thesis but no longer cheap. The discipline: VRT validates the category, but the underowned expression now sits further down at the component level (regulators, GaN), not the integrator. All US-listed.
Q6 — Demand-Curve Position
Tier ② — Capex guidance
Runway
Mid-early — climbing ↑
Metric
Watts per rack: 10–20x prior generation, still rising. 800V architecture transition just beginning (2027–2030+ adoption). Power content per GPU deployed is the climbing marker — and the GaN/SiC mix shift adds a second growth vector.
Evidence
Tier ② — rests on hyperscaler capex guidance ($200B+ committed) which is real but cuttable. Watch for tier ③ signals: multi-year cooling/power supply agreements would confirm the curve is earlier than the market prices.
EDA Software
liveUS-listed pure playssoftware duopolyhighest structural moat in the stack
Thesis
Every custom ASIC being designed by hyperscalers — Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA — requires Synopsys or Cadence tools. A two-company toll booth on the entire custom silicon trend. Fully US-listed, recurring revenue, switching cost measured in years. The surge in hyperscaler custom silicon is a leading indicator for EDA revenue 2–3 years forward.
Q1 — Physical inputs
PDK co-development is the structural moat
No physical inputs. Key dependency is Process Design Kits (PDKs) from TSMC — node-specific, co-developed between EDA vendor and foundry each process generation. PDK co-development creates switching friction even if a competitor matches on features. High-NA EUV transition creates a new PDK co-development cycle that resets switching costs for the next node generation.
Q2 — Co-purchases
EDA is manufacturing throughput, not just software
EDA licenses purchased 18–36 months before tape-out. But the deeper point: EDA is part of manufacturing throughput, not a software side-purchase. Mask generation, OPC (optical proximity correction), RET (resolution enhancement), and verification are all computational steps that gate whether a wafer can be patterned at all. High-NA, gate-all-around, and backside power delivery each increase the computational load dramatically — meaning EDA compute scales with node complexity, not just design starts. Custom ASIC surge is the leading revenue indicator 2–3 years forward.
Q3 — Constraint migration
Compute load explodes at High-NA / GAA / backside power
EDA is not a physical bottleneck — it scales with seats and compute. The constraint migrates to computational load: High-NA EUV, gate-all-around transistors, and backside power delivery each multiply the OPC/RET/verification compute required per design. This is a tailwind, not a ceiling — both Synopsys and Cadence are layering AI-driven design automation on top, expanding capacity while raising the value per seat. Growth story, different investment frame from the physical-constraint nodes.
Q4 — Supplier concentration the moat
~80% of advanced node EDA, two US companies
Synopsys and Cadence hold ~80%+ of advanced node EDA. Siemens EDA (#3) primarily covers older nodes. Switching cost is institutional knowledge embedded in design flows, IP libraries, and years of team training. No hyperscaler rebuilds chip design infrastructure on pricing alone. Highest switching cost in the entire stack — and both companies are fully US-listed.
Q5 — Economic Co-Traveler
Consensus — fully discovered
Co-traveler
Synopsys (SNPS), Cadence (CDNS) — but these are not hidden co-travelers; they are the node itself, and the market fully understands them as AI-silicon beneficiaries. No underowned adjacent name of comparable quality.
Underowned?
No — this fails the Q5 underowned test cleanly. Included for completeness and as a contrast: not every node has a hidden co-traveler. When the obvious names ARE the opportunity and they're fully priced, the honest call is that there's no Q5 edge here, only quality at a premium.
Q6 — Demand-Curve Position
Tier ③ — Binding (recurring)
Runway
Mid — structurally climbing ↑
Metric
Custom ASIC design starts (hyperscaler + auto + defense). Plus compute load per design rising with High-NA / GAA / backside power. Both the count of designs and the compute per design are climbing — a rare double tailwind.
Evidence
Recurring license revenue is tier ③ by nature — multi-year, embedded. Design starts lead revenue 2–3 years, making this a forward indicator. Not a constraint curve; a structural growth curve with long runway.
Grid & Data Center Construction
livequeue now exceeds total US grid capacity30–50% of 2026 capacity slipping to 2028helium compounding risk
Thesis — updated May 2026
Interconnection queues now exceed 2,100 GW — surpassing total US grid capacity — with analysts projecting 30–50% of planned 2026 data center capacity slipping to 2028. This is no longer an emerging risk. It is the binding constraint on AI infrastructure deployment pace. Compounding factor: the 2026 strikes on Qatari helium production (one-third of global supply) have doubled spot prices, and fabs in Taiwan and South Korea are now rationing helium for wafer cooling and leak detection.
Q1 — Physical inputs
Transformers — acute, no rapid fix
Large power transformers: US domestic capacity ~50 units/year, demand now multiples of that. Lead times 18–24 months and extending. Helium now added as a constrained physical input — spot prices doubled after Qatari production strikes in 2026, with fabs rationing supply. Transformer core steel concentrated in a handful of global mills with no rapid expansion path.
Q2 — Co-purchases
Construction BOM pulls through overlooked co-purchases
Data center construction BOM includes: backup generators (Caterpillar, Cummins), UPS systems (Vertiv, Eaton), fiber interconnect (Corning, Prysmian), HVAC at massive scale. Same analytical failure as the CPU miss — mechanical co-purchases of a primary capex wave that didn't get traced. These are US-listed, accessible names.
Q3 — Constraint migration macro risk
If grid doesn't clear — thesis migrates to nuclear
Interconnection queues at 3–7 years mean grid doesn't clear on normal timelines. Constraint migrates to nuclear (SMRs, plant restarts) and natural gas peakers as hyperscalers pursue behind-the-meter power. Microsoft, Google, and Amazon all have active nuclear agreements. This is a qualitatively different investment surface — energy, not semiconductors.
Q4 — Supplier concentration
Transformer oligopoly, no rapid capacity add
- Hitachi Energy — largest large transformer supplier globally
- ABB — second largest, European-headquartered
- Siemens Energy — significant grid infrastructure exposure
- SPX Transformer — primary US domestic manufacturer, severely capacity-limited
Q5 — Economic Co-Traveler
Underowned — energy adjacency
Co-traveler
The separate causal chain is energy, not semis. If grid binds, the demand migrates to independent power producers, nuclear (SMR developers, uranium), natural gas turbine makers (GE Vernova), and grid-equipment names (transformers, Quanta Services). A completely different sector benefiting from the same AI demand root.
Underowned?
Partially — GE Vernova and nuclear names have re-rated on the AI-power narrative, but the second-order plays (transformer-component suppliers, grid-construction labor) remain under-modeled. The framework's reach into energy is where its least-crowded US-listed ideas likely sit.
Q6 — Demand-Curve Position
Tier ③ — Binding commitment
Runway
Early — structural, multi-year ↑
Metric
Interconnection queue: 2,100+ GW, exceeding total US grid capacity. Transformer lead times 18–24 months and extending. 30–50% of planned 2026 data center capacity slipping to 2028 — the constraint is lengthening, not resolving.
Evidence
Tier ③ — signed interconnection agreements and hyperscaler nuclear deals (Microsoft, Google, Amazon) are binding multi-year commitments. The longest-runway node in the framework; physical buildout cannot be compressed.
Photomasks & High-NA EUV Transition
forming — next nodemapped May 20262027–2028 inflectionJapan duopolyinvisible to most investors
Why we're mapping this now — before it's acute
Photomasks are the stencils that pattern every wafer at every node. Nobody talks about them. The supply chain is a Japanese duopoly for EUV mask blanks (AGC and Shin-Etsu), and the High-NA EUV transition is forcing a new, more demanding supply constraint into view. Demand for High-NA reticles rises 40–60% per mask versus standard EUV. Scrap rates force fabs to discard up to 25% of EUV mask blanks at $50,000–$100,000 each. New capacity from Shin-Etsu's $545M Gunma project only arrives in 2026. This is the Q1 failure mode in formation: an upstream physical input to every TSMC node that is not being tracked because it hasn't broken yet.
Q1 — Physical inputs forming
EUV mask blanks — Japan duopoly, no alternatives
EUV photomasks require ultra-low-expansion (ULE) quartz substrates for thermal stability. Shin-Etsu and Tosoh control over 80% of ULE quartz supply. AGC and Shin-Etsu are the two primary qualified EUV mask blank suppliers globally. High-NA EUV requires larger reticles — 40–60% more mask area per chip — deepening the supply gap. Shin-Etsu's new $545M Gunma capacity arriving in 2026 but may be insufficient against accelerating demand. Defect densities at High-NA force up to 25% scrap at $50–100K per blank.
Q2 — Co-purchases
Mandatory for every wafer at every advanced node
Photomasks are purchased at the start of every chip design tape-out. Every new product requires a new mask set — typically 80–100 masks per chip at advanced nodes, costing $5–15M per set. High-NA transition will require entirely new mask sets — a forced refresh of existing inventory. The co-purchase signal here is design starts — same leading indicator as EDA licenses, 18–36 months ahead of volume production.
Q3 — Constraint migration
Migrates through each node transition
TSMC is deferring High-NA EUV purchase (at $400M/unit vs $200M for standard EUV) — extending Low-NA demand instead. This delays the High-NA photomask crunch but does not eliminate it. A12/A13 nodes targeted for 2029 without High-NA. A16 volume production delayed to 2027. The constraint tightens progressively with each node transition, not all at once — giving a defined monitoring timeline.
Q4 — Supplier concentration deepening
Qualified to two companies for leading-edge blanks
- AGC Inc. (Japan) — primary EUV mask blank supplier
- Shin-Etsu Chemical (Japan) — also in Tier 1 wafers and Tier 2 photochemicals — triple concentration risk
- Hoya Corporation (Japan) — specialty masks, expanding into High-NA
- Photronics (US, Nasdaq: PLAB) — only US-listed pure play photomask manufacturer
The Shin-Etsu triple concentration problem
Shin-Etsu Chemical now appears in three separate tiers of the TSMC supply chain simultaneously: Tier 1 as the largest silicon wafer supplier, Tier 2 as a primary photoresist supplier, and now in the photomask layer as the primary EUV mask blank supplier. A single disruption to Shin-Etsu — earthquake, regulatory action, capacity decision — cascades across wafers, chemistry, and mask supply in parallel. This is the highest single-company concentration risk in the entire framework.
Watch: TSMC High-NA Order
When TSMC commits to High-NA EUV orders, the photomask demand surge begins. ASML CFO flagged discussions close to concluding in Q2/Q3 2026.
Watch: Shin-Etsu Gunma Ramp
New capacity arriving 2026. Whether it's sufficient against High-NA demand determines whether this node becomes acute in 2027 or later.
Watch: Photronics (PLAB)
Only US-listed photomask manufacturer. Qualifies as the Q5 economic co-traveler for this node — visible, underowned, directly in the blast radius.
The qualification link to metrology
A photomask is only usable once it passes actinic (EUV-wavelength) inspection — and that inspection capability is itself concentrated. Lasertec dominates actinic mask inspection; KLA competes on wafer-side and pattern inspection. This means the photomask qualification chokepoint runs through the metrology node. The two forming nodes are coupled: mask supply doesn't bind in isolation, it binds at the qualification step that metrology controls. See the Metrology node for the inspection-side concentration.
Q5 — Economic Co-Traveler
Underowned — single US play
Co-traveler
Photronics (PLAB) — the only US-listed pure-play photomask manufacturer. Mask blanks are dominated by AGC and Shin-Etsu (Japan), but the merchant photomask layer has a US-accessible name that screens as a small-cap semi supplier, not an AI play.
Underowned?
Yes — small cap, low coverage, rarely discussed in AI-infrastructure contexts. The caution: PLAB is merchant masks, not the EUV mask-blank chokepoint itself (that's the Japanese duopoly). It's the accessible adjacency, not the core constraint — size the thesis accordingly.
Q6 — Demand-Curve Position
Tier ② — Capex guidance
Runway
Early — but not yet binding ⏸
Metric
High-NA reticle area: +40–60% per mask vs standard EUV. Masks per advanced chip: 80–100. The climbing marker is High-NA tool installs — but TSMC is deferring High-NA on cost, which delays the demand inflection to 2027–2028.
Evidence
Honest read: this is tier ② at best. The constraint is structural and real, but the demand timing depends on a High-NA transition that's being pushed out. Early on the curve, but the curve hasn't started climbing steeply yet. This is why it's "forming," not "live."
Metrology, Inspection & Process Control
forming — next nodemapped May 2026KLA ~58% monopolyUS-listedscales with complexity, not volume
Why this may be the most investable forming node
Metrology is the most ignored node in the stack — and unlike photomasks, the dominant player is a large, liquid, US-listed compounder. KLA commands ~58% of global process control, inspection, and metrology, and over 85% of optical wafer inspection — roughly 6.5x its nearest competitor. The structural key: inspection and metrology tools scale with process complexity, not wafer volume. More process steps, tighter tolerances, more 3D stacking — each adds permanent basis points to the process-control budget per wafer. KLA's revenue grows faster than wafer starts or total equipment spend.
Process Control Share
~58%
6.5x nearest competitor
Optical Inspection
>85%
near-monopoly segment
FY2025 Revenue
$12.2B
~24% YoY growth
2030 Revenue Target
$26B
management raised guidance
Q1 — Physical inputs
Optical and e-beam inspection systems
High-precision optical systems, e-beam columns, and the computational analytics layer that interprets defect data. The moat is not raw materials — it is decades of accumulated defect-detection algorithms and the reference library of known defect signatures. New entrants cannot replicate the data advantage even with comparable hardware. KLA invests >11% of revenue in R&D to widen this gap.
Q2 — Co-purchases complexity-scaled
Mandatory at every process step — and steps are multiplying
Every advanced node and every AI chip architecture requires proportionally more inspection. When KLA introduces EUV-based process control in DRAM, it adds ~100bp to the WFE budget. HBM stacked-die inspection adds another ~100bp. These are permanent increases, not one-time purchases. 2.5D/3D packaging (CoWoS, SoIC) expands the back-end process-control market directly — KLA's PCB and component inspection grew 61% YoY in Q1 FY2026 on advanced packaging demand.
Q3 — Constraint migration couples to photomask
Actinic mask inspection is the qualification chokepoint
High-NA EUV dramatically raises metrology requirements — stochastic defects at smaller geometries require ultra-sensitive e-beam and actinic inspection. This is where metrology couples to the photomask node: actinic (EUV-wavelength) mask inspection is the step that qualifies a mask for production. Lasertec (Japan) dominates actinic mask inspection specifically; KLA leads wafer-side and pattern inspection. The qualification constraint the whole framework keeps surfacing runs through this node.
Q4 — Supplier concentration
The cleanest monopoly in the stack
- KLA (US, Nasdaq: KLAC) — ~58% overall, >85% optical inspection, gaining share every year
- Applied Materials — distant #2 at <10%, share declining
- Lasertec (Japan) — dominant specifically in actinic EUV mask inspection
- Onto Innovation (US, Nasdaq: ONTO) — smaller, focused on packaging metrology and overlay
Bull case
Revenue scales with process complexity, not wafer volume — structurally faster growth than WFE
~58% share expanding, not defending — every competitor lost share in 2025
US-listed, liquid, large-cap compounder — fits the US mandate cleanly, no ADR friction
Each node transition and each AI architecture permanently raises process-control intensity
~30–40% recurring services revenue cushions WFE cyclicality
Inspection less exposed to China export restrictions than litho (ASML) or etch/deposition (LRCX/AMAT)
Bear case
Premium valuation — the quality is well understood; ~25% run since Jan 2026 prices much of the thesis
China revenue declined 41%→30% of mix; further BIS restrictions a $300–350M CY2026 headwind
Cyclical WFE exposure remains — services cushion the trough but don't eliminate it
Lasertec owns the actinic mask-inspection niche — KLA does not control the full qualification chokepoint
Fails the Q5 "underowned" test — this is a known quality name, not a hidden co-traveler
Watch: Process-Control Intensity
Each new node adds basis points to the WFE process-control budget. 2nm capturing more WFE share than 3nm is a step-function, not incremental.
Watch: Lasertec Actinic Position
If KLA closes the actinic mask-inspection gap, it captures the full qualification chokepoint. If Lasertec holds, the value splits.
Watch: Onto Innovation (ONTO)
The smaller US-listed name — more of a Q5 co-traveler than KLA. Packaging metrology exposure, lower visibility, smaller cap.
The honest framing — this one's already visible
Metrology is the strongest forming node analytically, but KLA fails the Q5 "underowned" test — it's a well-understood quality compounder, not a hidden upstream name. The genuine Q5 co-traveler here is Onto Innovation: smaller, less covered, packaging-metrology exposure. The discipline point: a node being correct and a node being underpriced are different questions. KLA may be the better business; ONTO may be the better Q5 expression. Separate the two.
Q5 — Economic Co-Traveler
Discovered — ONTO running
Co-traveler
KLA (KLAC) is the node — known quality compounder, fails the underowned test. Onto Innovation (ONTO) is the truer Q5 expression: smaller, packaging-metrology focused, lower coverage. Both US-listed, fitting the mandate.
Underowned?
ONTO was underowned — but ran ~$90→$300 on Dragonfly HBM-inspection demand and now carries a Strong Buy consensus. It's moved from hidden to discovered. The VRT discipline applies: a co-traveler that already ran can still be early if the demand curve has runway — but "underowned" no longer describes it. Watch a smaller, earlier name for the next expression.
Q6 — Demand-Curve Position
Tier ③ — Binding commitment
Runway
Mid-early — climbing ↑
Metric
Inspection passes per die rise with HBM layer count (8→16) and node shrink (3nm→2nm→A16). Process-control intensity adds ~100bp to WFE budget per major step. Onto's Dragonfly has $240M+ in HBM deals signed through 2027.
Evidence
Tier ③ — multi-year Dragonfly HBM agreements, KLA 2030 revenue target raised to $26B. The VRT test: ONTO ran ~$90→$300 before the framework surfaced it — but if inspection intensity per die is still climbing (it is), the runway ahead matters more than the chart behind. Early on the demand curve despite the price.